High definition microstructured Stencil masks.
Characteristics:
Our high-definition micropatterned stencil masks are made using the very versatile UV-LiGA process with photoresist features defining an inverted shape of the final part-geometry. Our stencil masks have tapered sidewalls in order to minimize the shadowing effect during the PVD- or CVD-coating processes.
1: SEM-image of Stencil-mask with 50µm holes and 15° sidewall-tapering.
2: SEM-image of Stencil-mask with 100µm holes and 15° sidewall-tapering.
3: SEM-image of Stencil-mask with comb-variation and 15° sidewall-tapering.
4: SEM-image of Stencil-mask with comb-variation and 15° sidewall-tapering.
5: SEM-image of Stencil-mask with USAF-target resolution-pattern and 15° sidewall-tapering.
6: SEM-image of Stencil-mask with Siemens-star resolution-pattern and 15° sidewall-tapering.
7: SEM-image of Stencil-mask with array of rectangular-frames and 15° sidewall-tapering.
8: SEM-image of Stencil-mask with array of rectangular-frames and 15° sidewall-tapering.
9: SEM-image-detail of Stencil-mask with array of rectangular-frames and 15° sidewall-tapering.
10: SEM-image-detail of Stencil-mask with array of rectangular-frames and 15° sidewall-tapering.
Material: Nickel, Nickel-Phos12 (580HV)
Applications: Hard mask during high-temperature PVD or CVD-processes
Specifications:
- Pattern size ≥ 5µm
- Nozzle thickness = 20 - 500µm
- Material: Nickel, Nickel-Phos12, stainless
- Aspect ratio = 5 - 6 (depends on pattern-design)
- EXCLUSIVE: Adjustable pattern-tapering up to 15°
- Manufacturing according to adapted LiGA-process
- Multilevel pattern available (e.g. increase part-stiffness)
- Alignment-precision: level-to-level ≤ 3μm
- Maximal patterned area = 200 x 200mm
- Parallelism Frontside-to-backside ≤ 10μm
- Available PVD-coatings
- Compatible photoresist for UV-lithography:
AZ positive resists, Microchem SU-8
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1. Convert customer data into Maskdesign
2. Fabrication of maskset
3. Lithography on substrates =» resist-mold
4. Prepare the resist-master for Ni-electroforming
5. Removal of resist and release from wafer